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TMC1103
Triple Video A/D Converter with Clamps
8-Bit, 50Msps Features
* * * * * * * * * * * * 8-bit resolution 50 Msps conversion rate Low power: 100mW per channel @ 20 Msps Integral track/hold Independent Input Clamps Independent clock inputs Integral and differential linearity error 0.5 LSB Differential phase 0.7 degree Differential gain 1.8% Single +5V power supply Three-state TTL/CMOS-compatible outputs Low cost
Applications
* * * * * * * Video digitizing (composite and Y-C) VGA and CCD digitizing LCD projection panels Image scanners Personal computer video boards Multimedia systems Low cost, high speed data conversion
Description
Incorporated into the TMC1103 are three analog-to-digital (A/D) converters, each with an independent clock, reference voltage and input clamp. Analog signals are converted to Triple 8-bit digital words at sample rates up to 50 Msps (Megasamples per second) per channel. Integral Track/Hold circuits deliver excellent performance on signals with full-scale spectral components up to 12 MHz. Innovative two-step conversion architecture and submicron CMOS technology reduce typical power dissipation to 100 mW per converter. Power is derived from a single +5 Volt power supply. Outputs are three-state outputs and TTL/CMOS-compatible. TMC1103 package is a 80-lead Metric Quad Flat Pack (MQFP). Performance specifications are guaranteed from 0C to 70C.
Block Diagram
RTA RBA VINA VCLPA CLPA RTB RBB VINB VCLPB CLPB RTC RBC VINC VCLPC CLPC Clamp 8-bit A/D Converter DA7-0 OEC CLKC
65-1103-01
Clamp
8-bit A/D Converter
DA7-0 OEA CLKA
Clamp
8-bit A/D Converter
DA7-0 OEB CLKB
Rev. 1.2.0
TMC1103
PRODUCT SPECIFICATION
Circuit Function
Within the TMC1103 are three 8-bit A/D converters, each employing two-step architecture to convert an analog input to a digital output at rates up to 50 Msps. Input signals are held in integral track/hold stages during the conversion process. Operation is pipelined, with one input sample taken and one output word provided for each CLKX cycle. Each of the three converters function identically. In the following descriptions `X' refers to a generic input/output or clock where `X' is equivalent to A, B or C. The first step in the conversion process is a coarse 4-bit quantization. This determines the range of the subsequent fine 4-bit quantization step. To eliminate spurious codes, the fine 4-bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse result to form a complete 8-bit result.
Analog Input
0.1F
VINX A/D Converter
VCLPX CLPX
65-1103-02
Input Clamp Circuit
Digital Inputs and Outputs
Sampling of the applied input signal occurs on the falling edge of the CLKX signal (Figure 1). Output data is delayed by 2 1/2 CLKX cycles and is valid following the rising edge of CLKX. Previous output data remains valid for tHO (Output Hold Time). New data becomes valid tD (Output Delay Time) after this rising edge of CLKX. Whenever the analog input signal is sampled and found to be at a level beyond the A/D conversion range, the output limits at 00h or FFh, as appropriate.
Analog Input and Voltage References
Each A/D accepts analog signals in the range RBX to RTX into digital data. Input signals outside this range produce "saturated" 00h or FFh output codes. The device will not be damaged by signals within the range AGND to VDDA. Input range is very flexible and extends from the +5 Volt power supply to ground. Nominal input range is 2 Volts, extending from 0.6V to 2.6V. Characterization and performance is specified over this range. However, the part will function with a full-scale range from 1.0V to 5.0V. A smaller input range may simplify analog signal conditioning circuitry, at the expense of additional noise sensitivity and some reduced differential linearity performance. External voltage reference sources are connected to the RTX and RBX pins. RBX can be grounded. Within each A/D converter is a reference resistor ladder comprising 255 resistors that are accessed by the TMC1103 comparators. RTX is connected to the top of the ladder, RBX to the bottom. Gain and offset errors are directly related to the accuracy and stability of the applied reference voltages.
Table 1. A/D Output Coding
Input Voltage RTX + 1 LSB RTX RTX - 1 LSB *** RBX + 128 LSB RBX + 127 LSB *** RBX + 1 LSB RBX RBX - 1 LSB
Note: 1 LSB = (RTX - RBX) / 255
Output FF FF FE *** 80 7F *** 01 00 00
Input Clamps
A clamp circuit is connected to the input pin VINX of each of the three A/D converters. With CLPX LOW, the input pin is clamped to the voltage at VCLPX. If CLPX is HIGH, the input pin is high impedance. Clamping adds an offset voltage to an AC coupled signal to adjust this signal's amplitude to the A/D converter input voltage range. The analog input is corrected through a 0.1mF capacitor to VINX. The source impedance of the analog source should be less than 50 Ohms. Current pulses through the capacitor over several clamp cycles until the voltage across the capacitor equals the difference between VCLPX and the voltage at the analog source during the clamping period. When the switch is open, the voltage on the coupling capacitor is added to the analog input, producing a a DC offset input signal.
The outputs of the TMC1103 are CMOS- and TTL-compatible, and are capable of driving four low-power Schottky TTL loads. An Output Enable control, OEX, places the A/D outputs in a high-impedance state when HIGH. The outputs are enabled when OEX is LOW.
Power and Ground
The TMC1103 operates from a single +5 Volt power supply. For optimum performance, an analog ground plane should be placed under the TMC1103 the AGND and DGND pins should be connected to the system analog ground plane.
2
PRODUCT SPECIFICATION
TMC1103
Pin Assignments
64 65 41 40 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name NC DA5 DA6 DA7 OEA VDD VDD NC CLKA NC VDDA VINA AGND RTA RBA VCLPA VCLPB VCLPC DGND DGND Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DGND DGND NC NC DGND DGND VDD CLPA CLPB CLPC NC DGND DGND DC0 DC1 DC2 DC3 DC4 DC5 DC6 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name DC7 OEC VDD VDD CLKC NC VDDA VINC AGND RTC RBC RBB RTB AGND VINB VDDA NC CLKB NC VDD Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VDD OEB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND NC DGND DGND DA0 DA1 DA2 DA3 DA4
80 1 24
65-1103-03
25
3
PRODUCT SPECIFICATION
TMC1103
Pin Descriptions
Pin Name A/D Converters VINA, VINB, VINC RTA, RTB, RTC RBA, RBB, RBC CLKA, CLKB, CLKC DA7-0 12, 55, 48 14, 53, 50 15, 52, 51 9, 58, 45 4, 3, 2, 80, 79, 78, 77, 76 63, 64, 65, 66, 67, 68, 69, 70 41, 40, 39, 38, 37, 36, 35, 34 5, 62, 42 RTX to RBX 2.6V 0.6V CMOS CMOS/ TTL CMOS/ TTL CMOS/ TTL CMOS Analog Inputs. The input voltage conversion range lies between the voltage applied to the RTX and RBX pins. Reference Voltage, Top Inputs. DC voltages applied to RTA, RTB and RTC define highest value of VINX. Reference Voltage, Bottom Inputs. DC voltages applied to RBA, RBB and RBC define lowest value of VINX. Clock Inputs. CMOS-compatible. VINX is sampled on the falling edge of CLKX. Data outputs, Converter A (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Data outputs, Converter B (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Data outputs, Converter C (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. Output Enable Inputs. CMOS-compatible. When LOW, the A/D output is enabled. When HIGH, the output is in a high-impedance state. Clamp Reference Voltage. One reference for each clamp. A VINX input is clamped to VCLPX when CLPX is low. Clamp Pulse Inputs. One input for each A/D clamp. When CLPX is low, the VINX input is clamped to the VCLPX clamp voltage. Analog Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. Digital Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. Analog Ground. Ground connections. These pins should be connected to the system analog ground plane. Digital Ground. Ground connections. These pins should be connected to the system analog ground plane. Pin Number Value Pin Function Description
DB7-0
DC7-0
OEA, OEB, OEC
Clamps VCLPA, VCLPB, VCLPB CLPA, CLPB, CLPC Power VDDA VDD 11, 47, 56 6, 7, 27, 28, 29, 30, 43, 44, 60, 61 13, 49, 54 16, 17, 18, 19, 20, 21, 22, 25, 26, 32, 33, 71, 72, 74, 75 1, 8, 10, 23, 24, 31, 46, 57, 59, 73 +5V +5V 16, 17, 18 28, 29, 30 RTX to RBX CMOS
AGND DGND
0.0V 0.0V
No Connect N/C open Not Connected.
4
PRODUCT SPECIFICATION
TMC1103
tSTD VINX Sample N Sample N+2
Sample N+3
Sample N+1 tPWL CLKX tDO tHO Hi-Z DX7-0 Data N-3 Data N-2 Data N-1 Data N tPWH 1/fS
tDIS
tENA
OEX
65-1103-04
Figure 1. Timing
Equivalent Circuits and Threshold Levels
VDD VDD
p Digital Input n
p Digital Output n
27011B 27014B
GND
GND
Figure 2. Equivalent Digital Input Circuit
Figure 3. Equivalent Digital Output Circuit
5
TMC1103
PRODUCT SPECIFICATION
Equivalent Circuits and Threshold Levels (continued)
VDDA VRT
VIN OE Three-State Outputs AGND 0.5V High Impedance tDIS 0.5V
tENA
2.0V 0.8V
7048B
29030
VRB
Figure 4. Equivalent Analog Input Circuit
Figure 5. Threshold Levels for Three-State Measurements
Absolute Maximum Ratings
Parameter Power Supply Voltages VDDA VDD VDDA AGND Digital Inputs Applied Voltage Forced current Analog Inputs Applied Voltage Forced current Digital Outputs Applied voltage Forced current Short circuit duration Temperature Operating, ambient Junction Lead, soldering Vapor Phase soldering Storage Electrostatic Discharge 10 seconds 1 minute Condition
(beyond which the device may be damaged)1 Min -0.5 -0.5 -0.5 -0.5 -0.5 -10.0 Typ Max +7.0 +7.0 +0.5 +0.5 VDD + 0.5 +10.0 VDDA+0.5 +10.0 VDD + 0.5 +6.0 1 second -20 110 +150 +300 +220 -65 +150 150 C C C C C V Unit V V V V V mA V mA V mA
Measured to AGND Measured to DGND Measured to VDD Measured to DGND Measured to DGND
Measured to AGND
-0.5 -10.0
Measured to DGND Single output in HIGH state to ground)
-0.5 -6.0
EIAJ test method
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
6
PRODUCT SPECIFICATION
TMC1103
Operating Conditions
Parameter VDD, VDDA AGND VRTX VRBX VRTX-VRBX VINX VCLPX VIH VIL IOH IOL TA Power Supply Voltage Analog Ground (Measured to DGND) Reference Voltage, Top Reference Voltage, Bottom Reference Voltage Differential Analog Input Range Clamp Reference Voltage, 50W max source Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 0 1.0 VRB 0 0.7 VDD GND VDD 0.3 VDD -4.0 4.0 70 Min. 4.75 -0.1 Nom 5.0 0 2.6 0.6 2.0 5.0 VRT Max. 5.25 0.1 VDDA Units V V V V V V V V V mA mA C
Electrical Characteristics
Parameter IDD Power Supply Current1 Conditions CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps fS = 40 Msps fS = 50 Msps IDDQ Power Supply Current, Quiescent VDD = VDDA = Max. CLKX = LOW CLKX = HIGH PD Total Power Dissipation1 CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps fS = 40 Msps fS = 50 Msps CAI RIN RREF ICB IIH IIL IOZH IOZL IOS Input Capacitance, Analog Input Resistance Reference Resistance Input Current, Analog Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output LOW Short-Circuit Current VDD = Max., VIN = VDD VDD = Max., VIN = 0V VDD = Max., VIN = VDD VDD = Max., VIN = VDD CLKX = LOW CLKX = HIGH 500 200 270 340 5 5 5 5 5 35 300 425 490 4 12 470 630 710 mW mW mW pF pF kW W mA mA mA mA mA mA 29 45 55 65 mA mA 70 94 105 90 120 135 mA mA mA Min. Typ1 Max. Units
7
TMC1103
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
Parameter VOH VOL CDI CDO Output Voltage, HIGH Output Voltage, LOW Digital Input Capacitance Digital Output Capacitance Conditions IOH = -2.5mA IOH = Max. IOL = Max. 4 10 Min. 3.5 2.4 0.4 10 Typ1 Max. Units V V V pF pF
Note: 1. Typical values with VDD = VDDA = Nom and TA = Nom, Maximum values with VDD = VDDA = Max. and TA = Min.
Switching Characteristics
Parameter fS Conversion Rate TMC1103-20 TMC1103-40 TMC1103-50 tPWH CLKX Pulsewidth, HIGH TMC1103-20 TMC1103-40 TMC1103-50 tPWL CLKX Pulsewidth, LOW TMC1103-20 TMC1103-40 TMC1103-50 EAP tSTO tSTS tCPW tCDLY tHO tDO tENA tDIS Aperture Error Sampling Time Offset Sampling Time Skew Clamp Pulse Width1 +20 < TA < +70C CLOAD = 15pF 2 100 9 14 27 42 300 Clamp Delay Time Output Hold Time Output Delay Time Output Enable Time Output Disable Time 1 8 8 7 30 2 150 5 400 ns ns ns ps ns ps mS ns ns ns ns ns 14 14 13 ns ns ns 20 40 50 Msps Msps Msps Conditions Min. Typ. Max. Units
8
PRODUCT SPECIFICATION
TMC1103
System Performance Characteristics
Parameter ELI ELD BW Integral Linearity Error, Independent Differential Linearity Error Bandwidth
1
Conditions VRT = 2.6V VRB = 0.6V TMC1203-20 TMC1203-40 TMC1203-50
Min.
Typ. 0.5 0.5
Max.
Units LSB LSB
10 12 12 -40 80
MHz MHz MHz mV
EOT
Offset Voltage, Top (RT - VIN for most positive code transition) Offset Voltage, Bottom (RB - VIN for most negative code transition) Offset Voltage, Clamp Differential Gain
VRT = 2.6V, VRB = 0.6V
EOB
VRT = 2.6V, VRB = 0.6V
-95
-30
mV
OFFCL dg
20 fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25C VRT = 2.6V, VRB = 0.6V fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25C VRT = 2.6V, VRB = 0.6V fN = 5.0 MHz fS = 20Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 2.48MHz fN = 6.98MHz fN = 10.0MHz fS = 40Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz fS = 50Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz 40 40 40 42 41 40 46 46 45 45 1.8
mV %
dp
Differential Phase
0.7
deg
XTALK SNR
Channel Crosstalk Signal-to-Noise Ratio
45
dB dB dB dB dB dB dB dB dB dB dB
9
TMC1103
PRODUCT SPECIFICATION
System Performance Characteristics (continued)
Parameter SFDR Spurious-Free Dynamic Range Conditions fS = 20Msps, VIN = 2V p-p fN = 1.24MHz fN = 2.48MHz fN = 6.98MHz fN = 10.0MHz fS = 40Msps, VIN = 2V p-p fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz fS = 50Msps, VIN = 2V p-p fN = 1.24MHz fN = 6.98MHz fN = 12.0MHz 46 40 37 dB dB dB 49 44 38 dB dB dB 53 48 44 40 dB dB dB dB Min. Typ. Max. Units
Notes: 1. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 2. Values shown in Typ. column are typical for VDD = VDDA = +5V and TA = 25C. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 5. Characteristics specified for VRT = 2.6V, VRB = 0.6V.
10
PRODUCT SPECIFICATION
TMC1103
Typical Performance Characteristics
35 30 25 IDD 20 15 10 5 0 0 10 20 30 fS (Msps) 40 50
65-1103-05
60 50 SFDR (dB) 40 30 20 10 0 0 5 10 15 20 25
65-1103-06
fS = 20Msps
fIN (Msps)
Figure 6. Typical IDD vs fS (Single A/D)
Figure 7. Typical SFDR vs fIN
50 40 SNR (dB) 30 20 10 0 0 5 10 15 20 25
65-1103-07
50 40 SNR (dB) 30 20 fS = 20Msps 10 0 0 1 2 VIN 3 4 5
65-1103-08
fS = 20Msps
fIN (MHz)
Figure 8. Typical SNR vs fIN
Figure 9. Typical SNR vs Full Scale Input Range
11
TMC1103
PRODUCT SPECIFICATION
Application Notes
The circuit in Figure 10 employs a band-gap reference to generate a variable RTX reference voltages for the TMC1103 as well as a bias voltage to offset the wideband input amplifiers to mid-range. The operational amplifier in the reference circuitry is a standard 741-type. The voltage reference at RTX can be adjusted from 0.0 to 2.4 volts while RBX is grounded. Schottky diodes can be used at VINX to restrict the wideband amplifier output to between -0.3V and VDD +0.3V. Diode protection is good practice to limit the analog input voltage at VINX to the safe operating range.
0.1F LM185-1.2 0.1F 1k1/2 +5V Gain Adjust 2k1/2 0.1F - 1k1/2 1k1/2 100 GREEN Video Input 0.1F VDDA + 201/2 RTA RTB RTC RBA RBB RBC + - 1k1/2 10k1/2 1k1/2 0.1F VINA VCLPA CLPA OEA CLKA VDD VDDP +5V +5V 0.1F
0.1F GREEN Digital Video Output
DA7-0
751/2
TMC1103
DB7-0 BLUE Digital Video Output
100 BLUE Video Input
+ - 1k1/2
0.1F VINB VCLPB CLPB
OEB CLKB
751/2
10k1/2
1k1/2 VCLPC CLPC + 0.1F VINC AGND VCLAMP 1k1/2 CLAMP
DC7-0 OEC CLKC DGND
RED Digital Video Output Pixel Clock
100 RED Video Input - 1k1/2 10k1/2
751/2
65-1103-09
Figure 10. Typical Interface Circuit - High Performance
Grounding
The TMC1103 has separate analog and digital circuits. To keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDD and VDDA) come from the same source, and that ground connections (DGND and AGND) be made to the analog ground plane, and as close as possible to the device pins. Power supply pins should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1103 should be referred to the system digital ground plane.
Printed Circuit Board Layout
Designing with high performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VN, RTX, RBX) as short as possible and as far as possible from all digital signals. The TMC1103 should be located close to the analog input connectors.
12
PRODUCT SPECIFICATION
TMC1103
2.
Segregate traces: * * * * A/D analog D/A analog Clocks Digital
5.
Treat analog inputs as transmission lines. Cleanly route traces over the ground plane bearing in mind that the return currents will flow through the ground plane beneath the traces. Do not route digital traces nearby. A few inches of digital trace less than a few line widths from an analog trace will cross-couple noise into adjacent analog circuits. 3. The power plane for the TMC1103 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC1103 is the same as that of the system's digital circuitry, power to the TMC1103 should be decoupled with ferrite beads and 0.1mF capacitors to reduce noise. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads.
Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the integrated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1mF ceramic capacitors. Lead lengths should be minimized. CLKX should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line, if needed, to eliminate overshoot and ringing.
6.
Related Products
* TMC1175A, TMC1275 8-Bit Video A/D Converters * TMC1173A, TMC1273 3V, Low-Power 8-Bit Video A/D Converters * TMC1203 Triple 8-bit A/D Converter * TMC3003/TMC3503 Triple Video D/A Converters * TMC2242B/TMC2243/TMC2246A Digital Filters
4.
13
TMC1103
PRODUCT SPECIFICATION
Notes:
14
PRODUCT SPECIFICATION
TMC1103
Mechanical Dimensions - 80-Lead MQFP Package
Symbol A A1 A2 B C D D1 E E1 e L N ND NE
a ccc
Inches Min. -- .010 .100 .012 .005 .904 .783 .667 Max. .134 -- .120 .018 .009 .923 .791 .687
Millimeters Min. -- .25 2.55 .30 .13 22.95 19.90 16.95 Max. 3.40 -- 3.05 .45 .23 23.45 20.10 17.45
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
3, 5 5
.547 .555 .0315 BSC .025 .041 80 24 16 0 -- 7 .004
13.90 14.10 .80 BSC .65 1.03 80 24 16 0 -- 7 0.10
4
D D1 e Datum Plane E1 E Pin 1 Identifier .13 (.005) R Min. B 0.063" Ref (1.60mm) Lead Detail See Lead Detail A A2 A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C L .20 (.008) Min. 0 Min. C a .13 (.30) R .005 (.012)
15
TMC1103
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC1103KLC20 TMC1103KLC40 TMC1103KLC50 Conversion Rate (Msps) 20 Msps 40 Msps 50 Msps Temperature Range TA = 0C to 70C TA = 0C to 70C TA = 0C to 70C Screening Commercial Commercial Commercial Package 80-Lead MQFP 80-Lead MQFP 80-Lead MQFP Package Marking 1103KLC20 1103KLC40 1103KLC50
6/22/98 0.0m 002 Stock# DS70001103

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